Microprocessor - II

1. Access time is faster for
a) ROM b) SRAM c) DRAM

2. In 8279 Strobed input mode, the control line goes low. The data on return lines is strobed in the ____.
a) FIFO byte by byte b) FILO byte by byte c) LIFO byte by byte
d) LILO byte by byte.

3. ___ bit in ICW1 indicates whether the 8259A is cascade mode or not?
a) LTIM=0 b) LTIM=1 c) SNGL=0 d) SNGL=1

4. In 8255, under the I/O mode of operation we have __ modes. Under which mode
will have the following features
i) A 5 bit control port is available.
ii) Three I/O lines are available at Port C.
a) 3, Mode2 b) 2, Mode 2 c) 4, Mode 3 d) 3, Mode 2

5. In ADC 0808 if _______ pin high enables output.
a) EOC b) I/P0-I/P7 c) SOC d) OE

6. In 8279, a scanned sensor matrix mode, if a sensor changes its state, the ___ line goes ____ to interrupt the CPU.
a) CS, high b) A0, high c) IRQ, high d) STB, high

7. In 8279 Status Word, data is read when ________ pins are low, and write to the
display RAM with ____________ are low.

a) A0, CS, RD & A0, WR, CS. b) CS, WR, A0 & A0, CS, RD
c) A0, RD & WR, CS d) CS, RD & A0, CS.

8. In 8279, the keyboard entries are debounced and stored in an _________, that is
further accessed by the CPU to read the key codes.
a) 8-bit FIFO b) 8-byte FIFO c) 16 byte FIFO d) 16 bit FIFO

9. The 8279 normally provides a maximum of _____ seven segment display
interface with CPU.
a) 8 b) 16 c) 32 d) 18

10. For the most Static RAM the write pulse width should be at least
a) 10ns b) 60ns c) 300ns d) 1µs
11. BURST refresh in DRAM is also called as
a) Concentrated refresh b) distributed refresh c) Hidden refresh d) none

12. For the most Static RAM the maximum access time is about
a) 1ns b) 10ns c) 100ns d) 1µs

13. Which of the following statements on DRAM are correct?
i) Page mode read operation is faster than RAS read.
ii) RAS input remains active during column address strobe.
iii) The row and column addresses are strobed into the internal buffers using RAS
and CAS inputs respectively.
a) i & iii b) i & ii c) all d) iii

14. 8086 microprocessor is interfaced to 8253 a programmable interval timer. The
maximum number by which the clock frequency on one of the timers is divided by
a) 216 b) 28 c) 210 d) 220

15. 8086 is interfaced to two 8259s (Programmable interrupt controllers). If 8259s
are in master slave configuration the number of interrupts available to the 8086
microprocessor is
a) 8 b) 16 c) 15 d) 64

Microprocessor

1. Which interrupt has the highest priority?
a) INTR b) TRAP c) RST6.5

2. In 8085 name the 16 bit registers?
a) Stack pointer b) Program counter c) a & b

3. Which of the following is hardware interrupts?
a) RST5.5, RST6.5, RST7.5 b) INTR, TRAP c) a & b

4. What is the RST for the TRAP?
a) RST5.5 b) RST4.5 c) RST4

5. What are level Triggering interrupts?
a) INTR&TRAP b)RST6.5&RST5.5 c)RST7.5&RST6.5

6. Which interrupt is not level sensitive in 8085?
a) RST6.5 is a raising edge-trigging interrupt.
b) RST7.5 is a raising edge-trigging interrupt.
c) a & b.

7. What are software interrupts?
a) RST 0 - 7 b) RST 5.5 - 7.5 c) INTR, TRAP

8. Which stack is used in 8085?
a) FIFO b) LIFO c) FILO

9. Why 8085 processor is called an 8 bit processor?
a) Because 8085 processor has 8 bit ALU.
b) Because 8085 processor has 8 bit data bus.
c) a & b.

10. What is SIM?
a) Select Interrupt Mask b) Sorting Interrupt Mask c) Set Interrupt Mask.

11. RIM is used to check whether, ______
a) The write operation is done or not
b) The interrupt is Masked or not
c) a & b

12. What is meant by Maskable interrupts?
a) An interrupt which can never be turned off.
b) An interrupt that can be turned off by the programmer.
c) none

13. In 8086, Example for Non maskable interrupts are
a) Trap b) RST6.5 c) INTR

14. What does microprocessor speed depends on?
a) Clock b) Data bus width c) Address bus width

15. Can ROM be used as stack?
a) Yes b) No c) sometimes yes, sometimes no

16. Which processor structure is pipelined?
a) all x80 processors b) all x85 processors c) all x86 processors

17. Address line for RST3 is?
a) 0020H b) 0028H c) 0018H

18. In 8086 the overflow flag is set when
a) The sum is more than 16 bits
b) Signed numbers go out of their range after an arithmetic operation
c) Carry and sign flags are set
d) During subtraction

19. The advantage of memory mapped I/O over I/O mapped I/O is,
a) Faster
b) Many instructions supporting memory mapped I/O
c) Require a bigger address decoder
d) All the above

20. BHE of 8086 microprocessor signal is used to interface the
a) Even bank memory
b) Odd bank memory
c) I/O
d) DMA

21. In 8086 microprocessor the following has the highest priority among all type
interrupts.
a) NMI
b) DIV 0
c) TYPE 255
d) OVER FLOW

22. In 8086 microprocessor one of the following statements is not true.
a) Coprocessor is interfaced in MAX mode
b) Coprocessor is interfaced in MIN mode
c) I/O can be interfaced in MAX / MIN mode
d) Supports pipelining

23. 8088 microprocessor differs with 8086 microprocessor in
a) Data width on the output
b) Address capability
c) Support of coprocessor
d) Support of MAX / MIN mode

24. Address line for TRAP is?
a) 0023H b) 0024H c) 0033H